Static Timing Analysis

Project : grbl_lcd
Build Time : 09/21/17 14:51:44
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
Clock_1(fixed-function) Clock_1(fixed-function) 1.200 MHz 1.200 MHz N/A
Clock_LCD_Update(routed) Clock_LCD_Update(routed) 8.000  Hz 8.000  Hz N/A
Clock_Pen_Move(routed) Clock_Pen_Move(routed) 15.873  Hz 15.873  Hz N/A
CyBUS_CLK(fixed-function) CyBUS_CLK(fixed-function) 24.000 MHz 24.000 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 46.564 MHz
Clock_1 CyMASTER_CLK 1.200 MHz 1.200 MHz N/A
UART_BusServo_IntClock CyMASTER_CLK 923.077 kHz 923.077 kHz 45.269 MHz
UART_IntClock CyMASTER_CLK 923.077 kHz 923.077 kHz 44.705 MHz
Clock_Step_Pulse CyMASTER_CLK 250.000 kHz 250.000 kHz N/A
Clock_Pen_Move CyMASTER_CLK 15.873  Hz 15.873  Hz N/A
Clock_Lim_DB CyMASTER_CLK 10.000  Hz 10.000  Hz N/A
Clock_Sw_DB CyMASTER_CLK 10.000  Hz 10.000  Hz 142.796 MHz
Clock_LCD_Update CyMASTER_CLK 8.000  Hz 8.000  Hz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 1e+008ns(10  Hz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\/q \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_1\/main_0 142.796 MHz 7.003 99999992.997
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell66 U(1,0) 1 \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\ \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\/clock_0 \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\/q 1.250
Route 1 \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\ \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\/q \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_1\/main_0 2.243
macrocell67 U(1,0) 1 \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_1\ SETUP 3.510
Clock Skew 0.000
\Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\/q Net_300/main_0 142.796 MHz 7.003 99999992.997
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell66 U(1,0) 1 \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\ \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\/clock_0 \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\/q 1.250
Route 1 \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\ \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\/q Net_300/main_0 2.243
macrocell68 U(1,0) 1 Net_300 SETUP 3.510
Clock Skew 0.000
\Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_1\/q Net_300/main_1 142.939 MHz 6.996 99999993.004
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell67 U(1,0) 1 \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_1\ \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_1\/clock_0 \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_1\/q 1.250
Route 1 \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_1\ \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_1\/q Net_300/main_1 2.236
macrocell68 U(1,0) 1 Net_300 SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/ff0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 46.564 MHz 21.476 20.191
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/clock \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/ff0 0.670
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.ff0__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/ff0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ff0i 0.000
datapathcell5 U(2,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ff0i \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/f0_comb 2.720
Route 1 \QuadDec:Cnt16:CounterUDB:overflow\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/f0_comb \QuadDec:Cnt16:CounterUDB:reload\/main_2 2.766
macrocell17 U(2,2) 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/main_2 \QuadDec:Cnt16:CounterUDB:reload\/q 3.350
Route 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/q \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.610
datapathcell4 U(3,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 5.130
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell5 U(2,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 4.230
Clock Skew 0.000
\QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 46.642 MHz 21.440 20.227
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/clock \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 0.760
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.z0__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0i 0.000
datapathcell5 U(2,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0i \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb 2.740
Route 1 \QuadDec:Cnt16:CounterUDB:status_1\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb \QuadDec:Cnt16:CounterUDB:reload\/main_1 2.620
macrocell17 U(2,2) 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/main_1 \QuadDec:Cnt16:CounterUDB:reload\/q 3.350
Route 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/q \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.610
datapathcell4 U(3,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 5.130
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell5 U(2,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 4.230
Clock Skew 0.000
\QuadDec:Net_1203\/q \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 46.718 MHz 21.405 20.262
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell59 U(2,2) 1 \QuadDec:Net_1203\ \QuadDec:Net_1203\/clock_0 \QuadDec:Net_1203\/q 1.250
Route 1 \QuadDec:Net_1203\ \QuadDec:Net_1203\/q \QuadDec:Cnt16:CounterUDB:count_enable\/main_2 4.360
macrocell21 U(2,3) 1 \QuadDec:Cnt16:CounterUDB:count_enable\ \QuadDec:Cnt16:CounterUDB:count_enable\/main_2 \QuadDec:Cnt16:CounterUDB:count_enable\/q 3.350
Route 1 \QuadDec:Cnt16:CounterUDB:count_enable\ \QuadDec:Cnt16:CounterUDB:count_enable\/q \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_1 3.085
datapathcell4 U(3,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 5.130
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell5 U(2,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 4.230
Clock Skew 0.000
\QuadDec:Net_1260\/q \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 48.773 MHz 20.503 21.164
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell62 U(3,2) 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/clock_0 \QuadDec:Net_1260\/q 1.250
Route 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/q \QuadDec:Cnt16:CounterUDB:reload\/main_0 3.933
macrocell17 U(2,2) 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/main_0 \QuadDec:Cnt16:CounterUDB:reload\/q 3.350
Route 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/q \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.610
datapathcell4 U(3,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 5.130
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell5 U(2,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 4.230
Clock Skew 0.000
\QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/f0_comb \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 49.295 MHz 20.286 21.381
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/clock \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/f0_comb 2.200
Route 1 \QuadDec:Cnt16:CounterUDB:overflow\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/f0_comb \QuadDec:Cnt16:CounterUDB:reload\/main_2 2.766
macrocell17 U(2,2) 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/main_2 \QuadDec:Cnt16:CounterUDB:reload\/q 3.350
Route 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/q \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.610
datapathcell4 U(3,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 5.130
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell5 U(2,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 4.230
Clock Skew 0.000
\QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 49.432 MHz 20.230 21.437
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/clock \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb 2.290
Route 1 \QuadDec:Cnt16:CounterUDB:status_1\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb \QuadDec:Cnt16:CounterUDB:reload\/main_1 2.620
macrocell17 U(2,2) 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/main_1 \QuadDec:Cnt16:CounterUDB:reload\/q 3.350
Route 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/q \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.610
datapathcell4 U(3,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 5.130
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell5 U(2,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 4.230
Clock Skew 0.000
\QuadDec:Cnt16:CounterUDB:count_stored_i\/q \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 51.690 MHz 19.346 22.321
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell58 U(2,3) 1 \QuadDec:Cnt16:CounterUDB:count_stored_i\ \QuadDec:Cnt16:CounterUDB:count_stored_i\/clock_0 \QuadDec:Cnt16:CounterUDB:count_stored_i\/q 1.250
Route 1 \QuadDec:Cnt16:CounterUDB:count_stored_i\ \QuadDec:Cnt16:CounterUDB:count_stored_i\/q \QuadDec:Cnt16:CounterUDB:count_enable\/main_1 2.301
macrocell21 U(2,3) 1 \QuadDec:Cnt16:CounterUDB:count_enable\ \QuadDec:Cnt16:CounterUDB:count_enable\/main_1 \QuadDec:Cnt16:CounterUDB:count_enable\/q 3.350
Route 1 \QuadDec:Cnt16:CounterUDB:count_enable\ \QuadDec:Cnt16:CounterUDB:count_enable\/q \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_1 3.085
datapathcell4 U(3,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 5.130
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell5 U(2,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 4.230
Clock Skew 0.000
\QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\/control_7 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 51.760 MHz 19.320 22.347
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,3) 1 \QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\ \QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\/clock \QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\/control_7 1.210
Route 1 \QuadDec:Cnt16:CounterUDB:control_7\ \QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\/control_7 \QuadDec:Cnt16:CounterUDB:count_enable\/main_0 2.315
macrocell21 U(2,3) 1 \QuadDec:Cnt16:CounterUDB:count_enable\ \QuadDec:Cnt16:CounterUDB:count_enable\/main_0 \QuadDec:Cnt16:CounterUDB:count_enable\/q 3.350
Route 1 \QuadDec:Cnt16:CounterUDB:count_enable\ \QuadDec:Cnt16:CounterUDB:count_enable\/q \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_1 3.085
datapathcell4 U(3,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 5.130
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell5 U(2,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 4.230
Clock Skew 0.000
\QuadDec:Net_1260\/q \QuadDec:Net_1251\/main_7 52.469 MHz 19.059 22.608
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell62 U(3,2) 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/clock_0 \QuadDec:Net_1260\/q 1.250
Route 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/q \QuadDec:Net_1251_split\/main_1 8.727
macrocell57 U(3,0) 1 \QuadDec:Net_1251_split\ \QuadDec:Net_1251_split\/main_1 \QuadDec:Net_1251_split\/q 3.350
Route 1 \QuadDec:Net_1251_split\ \QuadDec:Net_1251_split\/q \QuadDec:Net_1251\/main_7 2.222
macrocell52 U(3,0) 1 \QuadDec:Net_1251\ SETUP 3.510
Clock Skew 0.000
\QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/ff0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 55.018 MHz 18.176 23.491
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/clock \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/ff0 0.670
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.ff0__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/ff0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ff0i 0.000
datapathcell5 U(2,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ff0i \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/f0_comb 2.720
Route 1 \QuadDec:Cnt16:CounterUDB:overflow\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/f0_comb \QuadDec:Cnt16:CounterUDB:reload\/main_2 2.766
macrocell17 U(2,2) 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/main_2 \QuadDec:Cnt16:CounterUDB:reload\/q 3.350
Route 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/q \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.610
datapathcell4 U(3,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ SETUP 6.060
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 62.520 MHz 15.995 25.672
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_15 Rx_1(0)/fb \UART:BUART:rx_postpoll\/main_0 4.931
macrocell6 U(0,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.235
datapathcell3 U(0,0) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_0\/main_5 88.511 MHz 11.298 30.369
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_15 Rx_1(0)/fb \UART:BUART:rx_state_0\/main_5 5.779
macrocell41 U(0,1) 1 \UART:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_2\/main_5 88.511 MHz 11.298 30.369
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_15 Rx_1(0)/fb \UART:BUART:rx_state_2\/main_5 5.779
macrocell44 U(0,1) 1 \UART:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb MODIN1_1/main_2 95.694 MHz 10.450 31.217
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_15 Rx_1(0)/fb MODIN1_1/main_2 4.931
macrocell47 U(0,0) 1 MODIN1_1 SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb MODIN1_0/main_2 95.694 MHz 10.450 31.217
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_15 Rx_1(0)/fb MODIN1_0/main_2 4.931
macrocell48 U(0,0) 1 MODIN1_0 SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_status_3\/main_5 95.767 MHz 10.442 31.225
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_15 Rx_1(0)/fb \UART:BUART:rx_status_3\/main_5 4.923
macrocell49 U(0,0) 1 \UART:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_last\/main_0 95.767 MHz 10.442 31.225
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_15 Rx_1(0)/fb \UART:BUART:rx_last\/main_0 4.923
macrocell50 U(0,0) 1 \UART:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_BusServo:BUART:tx_state_1\/q \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 45.269 MHz 22.090 1061.243
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell72 U(3,3) 1 \UART_BusServo:BUART:tx_state_1\ \UART_BusServo:BUART:tx_state_1\/clock_0 \UART_BusServo:BUART:tx_state_1\/q 1.250
Route 1 \UART_BusServo:BUART:tx_state_1\ \UART_BusServo:BUART:tx_state_1\/q \UART_BusServo:BUART:counter_load_not\/main_0 6.189
macrocell25 U(2,4) 1 \UART_BusServo:BUART:counter_load_not\ \UART_BusServo:BUART:counter_load_not\/main_0 \UART_BusServo:BUART:counter_load_not\/q 3.350
Route 1 \UART_BusServo:BUART:counter_load_not\ \UART_BusServo:BUART:counter_load_not\/q \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 5.111
datapathcell7 U(2,0) 1 \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 47.019 MHz 21.268 1062.065
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(2,0) 1 \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_BusServo:BUART:tx_bitclk_enable_pre\ \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_BusServo:BUART:counter_load_not\/main_2 6.427
macrocell25 U(2,4) 1 \UART_BusServo:BUART:counter_load_not\ \UART_BusServo:BUART:counter_load_not\/main_2 \UART_BusServo:BUART:counter_load_not\/q 3.350
Route 1 \UART_BusServo:BUART:counter_load_not\ \UART_BusServo:BUART:counter_load_not\/q \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 5.111
datapathcell7 U(2,0) 1 \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_BusServo:BUART:tx_state_2\/q \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 47.840 MHz 20.903 1062.430
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell74 U(2,3) 1 \UART_BusServo:BUART:tx_state_2\ \UART_BusServo:BUART:tx_state_2\/clock_0 \UART_BusServo:BUART:tx_state_2\/q 1.250
Route 1 \UART_BusServo:BUART:tx_state_2\ \UART_BusServo:BUART:tx_state_2\/q \UART_BusServo:BUART:counter_load_not\/main_3 5.002
macrocell25 U(2,4) 1 \UART_BusServo:BUART:counter_load_not\ \UART_BusServo:BUART:counter_load_not\/main_3 \UART_BusServo:BUART:counter_load_not\/q 3.350
Route 1 \UART_BusServo:BUART:counter_load_not\ \UART_BusServo:BUART:counter_load_not\/q \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 5.111
datapathcell7 U(2,0) 1 \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_BusServo:BUART:tx_state_0\/q \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 51.138 MHz 19.555 1063.778
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell73 U(3,4) 1 \UART_BusServo:BUART:tx_state_0\ \UART_BusServo:BUART:tx_state_0\/clock_0 \UART_BusServo:BUART:tx_state_0\/q 1.250
Route 1 \UART_BusServo:BUART:tx_state_0\ \UART_BusServo:BUART:tx_state_0\/q \UART_BusServo:BUART:counter_load_not\/main_1 3.654
macrocell25 U(2,4) 1 \UART_BusServo:BUART:counter_load_not\ \UART_BusServo:BUART:counter_load_not\/main_1 \UART_BusServo:BUART:counter_load_not\/q 3.350
Route 1 \UART_BusServo:BUART:counter_load_not\ \UART_BusServo:BUART:counter_load_not\/q \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 5.111
datapathcell7 U(2,0) 1 \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_BusServo:BUART:tx_state_1\/q \UART_BusServo:BUART:sTX:TxShifter:u0\/cs_addr_2 65.295 MHz 15.315 1068.018
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell72 U(3,3) 1 \UART_BusServo:BUART:tx_state_1\ \UART_BusServo:BUART:tx_state_1\/clock_0 \UART_BusServo:BUART:tx_state_1\/q 1.250
Route 1 \UART_BusServo:BUART:tx_state_1\ \UART_BusServo:BUART:tx_state_1\/q \UART_BusServo:BUART:sTX:TxShifter:u0\/cs_addr_2 8.055
datapathcell6 U(3,1) 1 \UART_BusServo:BUART:sTX:TxShifter:u0\ SETUP 6.010
Clock Skew 0.000
\UART_BusServo:BUART:tx_state_0\/q \UART_BusServo:BUART:sTX:TxShifter:u0\/cs_addr_1 67.751 MHz 14.760 1068.573
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell73 U(3,4) 1 \UART_BusServo:BUART:tx_state_0\ \UART_BusServo:BUART:tx_state_0\/clock_0 \UART_BusServo:BUART:tx_state_0\/q 1.250
Route 1 \UART_BusServo:BUART:tx_state_0\ \UART_BusServo:BUART:tx_state_0\/q \UART_BusServo:BUART:sTX:TxShifter:u0\/cs_addr_1 7.500
datapathcell6 U(3,1) 1 \UART_BusServo:BUART:sTX:TxShifter:u0\ SETUP 6.010
Clock Skew 0.000
\UART_BusServo:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_BusServo:BUART:sTX:TxSts\/status_0 68.442 MHz 14.611 1068.722
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(3,1) 1 \UART_BusServo:BUART:sTX:TxShifter:u0\ \UART_BusServo:BUART:sTX:TxShifter:u0\/clock \UART_BusServo:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART_BusServo:BUART:tx_fifo_empty\ \UART_BusServo:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_BusServo:BUART:tx_status_0\/main_3 4.256
macrocell26 U(3,3) 1 \UART_BusServo:BUART:tx_status_0\ \UART_BusServo:BUART:tx_status_0\/main_3 \UART_BusServo:BUART:tx_status_0\/q 3.350
Route 1 \UART_BusServo:BUART:tx_status_0\ \UART_BusServo:BUART:tx_status_0\/q \UART_BusServo:BUART:sTX:TxSts\/status_0 2.925
statusicell8 U(3,4) 1 \UART_BusServo:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART_BusServo:BUART:tx_state_0\/q \UART_BusServo:BUART:sTX:TxSts\/status_0 70.156 MHz 14.254 1069.079
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell73 U(3,4) 1 \UART_BusServo:BUART:tx_state_0\ \UART_BusServo:BUART:tx_state_0\/clock_0 \UART_BusServo:BUART:tx_state_0\/q 1.250
Route 1 \UART_BusServo:BUART:tx_state_0\ \UART_BusServo:BUART:tx_state_0\/q \UART_BusServo:BUART:tx_status_0\/main_1 6.229
macrocell26 U(3,3) 1 \UART_BusServo:BUART:tx_status_0\ \UART_BusServo:BUART:tx_status_0\/main_1 \UART_BusServo:BUART:tx_status_0\/q 3.350
Route 1 \UART_BusServo:BUART:tx_status_0\ \UART_BusServo:BUART:tx_status_0\/q \UART_BusServo:BUART:sTX:TxSts\/status_0 2.925
statusicell8 U(3,4) 1 \UART_BusServo:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART_BusServo:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_BusServo:BUART:tx_state_0\/main_3 72.548 MHz 13.784 1069.549
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(3,1) 1 \UART_BusServo:BUART:sTX:TxShifter:u0\ \UART_BusServo:BUART:sTX:TxShifter:u0\/clock \UART_BusServo:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART_BusServo:BUART:tx_fifo_empty\ \UART_BusServo:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_BusServo:BUART:tx_state_0\/main_3 6.694
macrocell73 U(3,4) 1 \UART_BusServo:BUART:tx_state_0\ SETUP 3.510
Clock Skew 0.000
\UART_BusServo:BUART:tx_state_1\/q \UART_BusServo:BUART:txn\/main_1 74.783 MHz 13.372 1069.961
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell72 U(3,3) 1 \UART_BusServo:BUART:tx_state_1\ \UART_BusServo:BUART:tx_state_1\/clock_0 \UART_BusServo:BUART:tx_state_1\/q 1.250
Route 1 \UART_BusServo:BUART:tx_state_1\ \UART_BusServo:BUART:tx_state_1\/q \UART_BusServo:BUART:txn\/main_1 8.612
macrocell71 U(3,1) 1 \UART_BusServo:BUART:txn\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 44.705 MHz 22.369 1060.964
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell36 U(2,1) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:counter_load_not\/main_0 8.732
macrocell2 U(1,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_0 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.847
datapathcell2 U(1,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.309 MHz 21.594 1061.739
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell37 U(2,1) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:counter_load_not\/main_1 7.957
macrocell2 U(1,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_1 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.847
datapathcell2 U(1,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.915 MHz 21.315 1062.018
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell38 U(2,1) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:counter_load_not\/main_3 7.678
macrocell2 U(1,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_3 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.847
datapathcell2 U(1,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:sRX:RxBitCounter\/load 54.002 MHz 18.518 1064.815
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell40 U(0,0) 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/clock_0 \UART:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:rx_counter_load\/main_0 6.246
macrocell5 U(0,1) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_0 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.312
count7cell U(0,1) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:TxShifter:u0\/cs_addr_2 57.172 MHz 17.491 1065.842
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell36 U(2,1) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:sTX:TxShifter:u0\/cs_addr_2 10.231
datapathcell1 U(2,4) 1 \UART:BUART:sTX:TxShifter:u0\ SETUP 6.010
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 58.803 MHz 17.006 1066.327
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:counter_load_not\/main_2 4.429
macrocell2 U(1,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_2 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.847
datapathcell2 U(1,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_state_1\/q \UART:BUART:txn\/main_1 60.085 MHz 16.643 1066.690
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell36 U(2,1) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:txn\/main_1 11.883
macrocell35 U(2,4) 1 \UART:BUART:txn\ SETUP 3.510
Clock Skew 0.000
\UART:BUART:tx_bitclk\/q \UART:BUART:txn\/main_6 62.189 MHz 16.080 1067.253
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell39 U(1,0) 1 \UART:BUART:tx_bitclk\ \UART:BUART:tx_bitclk\/clock_0 \UART:BUART:tx_bitclk\/q 1.250
Route 1 \UART:BUART:tx_bitclk\ \UART:BUART:tx_bitclk\/q \UART:BUART:txn\/main_6 11.320
macrocell35 U(2,4) 1 \UART:BUART:txn\ SETUP 3.510
Clock Skew 0.000
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:sTX:TxSts\/status_0 62.228 MHz 16.070 1067.263
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,4) 1 \UART:BUART:sTX:TxShifter:u0\ \UART:BUART:sTX:TxShifter:u0\/clock \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART:BUART:tx_fifo_empty\ \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:tx_status_0\/main_3 6.329
macrocell3 U(3,1) 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/main_3 \UART:BUART:tx_status_0\/q 3.350
Route 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/q \UART:BUART:sTX:TxSts\/status_0 2.311
statusicell1 U(3,1) 1 \UART:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:sRX:RxBitCounter\/load 62.909 MHz 15.896 1067.437
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell43 U(0,1) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_counter_load\/main_2 3.624
macrocell5 U(0,1) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_2 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.312
count7cell U(0,1) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_1\/q Net_300/main_1 3.486
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell67 U(1,0) 1 \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_1\ \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_1\/clock_0 \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_1\/q 1.250
Route 1 \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_1\ \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_1\/q Net_300/main_1 2.236
macrocell68 U(1,0) 1 Net_300 HOLD 0.000
Clock Skew 0.000
\Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\/q \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_1\/main_0 3.493
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell66 U(1,0) 1 \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\ \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\/clock_0 \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\/q 1.250
Route 1 \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\ \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\/q \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_1\/main_0 2.243
macrocell67 U(1,0) 1 \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_1\ HOLD 0.000
Clock Skew 0.000
\Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\/q Net_300/main_0 3.493
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell66 U(1,0) 1 \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\ \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\/clock_0 \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\/q 1.250
Route 1 \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\ \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\/q Net_300/main_0 2.243
macrocell68 U(1,0) 1 Net_300 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 2.140
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/clock \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 2.140
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell5 U(2,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\QuadDec:bQuadDec:quad_A_delayed_2\/q \QuadDec:bQuadDec:quad_A_filt\/main_2 3.484
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(2,0) 1 \QuadDec:bQuadDec:quad_A_delayed_2\ \QuadDec:bQuadDec:quad_A_delayed_2\/clock_0 \QuadDec:bQuadDec:quad_A_delayed_2\/q 1.250
Route 1 \QuadDec:bQuadDec:quad_A_delayed_2\ \QuadDec:bQuadDec:quad_A_delayed_2\/q \QuadDec:bQuadDec:quad_A_filt\/main_2 2.234
macrocell60 U(2,0) 1 \QuadDec:bQuadDec:quad_A_filt\ HOLD 0.000
Clock Skew 0.000
\QuadDec:bQuadDec:quad_A_delayed_1\/q \QuadDec:bQuadDec:quad_A_delayed_2\/main_0 3.488
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(2,0) 1 \QuadDec:bQuadDec:quad_A_delayed_1\ \QuadDec:bQuadDec:quad_A_delayed_1\/clock_0 \QuadDec:bQuadDec:quad_A_delayed_1\/q 1.250
Route 1 \QuadDec:bQuadDec:quad_A_delayed_1\ \QuadDec:bQuadDec:quad_A_delayed_1\/q \QuadDec:bQuadDec:quad_A_delayed_2\/main_0 2.238
macrocell31 U(2,0) 1 \QuadDec:bQuadDec:quad_A_delayed_2\ HOLD 0.000
Clock Skew 0.000
\QuadDec:bQuadDec:quad_A_delayed_1\/q \QuadDec:bQuadDec:quad_A_filt\/main_1 3.488
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(2,0) 1 \QuadDec:bQuadDec:quad_A_delayed_1\ \QuadDec:bQuadDec:quad_A_delayed_1\/clock_0 \QuadDec:bQuadDec:quad_A_delayed_1\/q 1.250
Route 1 \QuadDec:bQuadDec:quad_A_delayed_1\ \QuadDec:bQuadDec:quad_A_delayed_1\/q \QuadDec:bQuadDec:quad_A_filt\/main_1 2.238
macrocell60 U(2,0) 1 \QuadDec:bQuadDec:quad_A_filt\ HOLD 0.000
Clock Skew 0.000
\QuadDec:bQuadDec:quad_B_delayed_1\/q \QuadDec:bQuadDec:quad_B_delayed_2\/main_0 3.544
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell33 U(3,4) 1 \QuadDec:bQuadDec:quad_B_delayed_1\ \QuadDec:bQuadDec:quad_B_delayed_1\/clock_0 \QuadDec:bQuadDec:quad_B_delayed_1\/q 1.250
Route 1 \QuadDec:bQuadDec:quad_B_delayed_1\ \QuadDec:bQuadDec:quad_B_delayed_1\/q \QuadDec:bQuadDec:quad_B_delayed_2\/main_0 2.294
macrocell34 U(3,4) 1 \QuadDec:bQuadDec:quad_B_delayed_2\ HOLD 0.000
Clock Skew 0.000
\QuadDec:bQuadDec:quad_B_delayed_1\/q \QuadDec:bQuadDec:quad_B_filt\/main_1 3.544
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell33 U(3,4) 1 \QuadDec:bQuadDec:quad_B_delayed_1\ \QuadDec:bQuadDec:quad_B_delayed_1\/clock_0 \QuadDec:bQuadDec:quad_B_delayed_1\/q 1.250
Route 1 \QuadDec:bQuadDec:quad_B_delayed_1\ \QuadDec:bQuadDec:quad_B_delayed_1\/q \QuadDec:bQuadDec:quad_B_filt\/main_1 2.294
macrocell61 U(3,4) 1 \QuadDec:bQuadDec:quad_B_filt\ HOLD 0.000
Clock Skew 0.000
\QuadDec:bQuadDec:quad_B_delayed_0\/q \QuadDec:bQuadDec:quad_B_delayed_1\/main_0 3.557
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(2,4) 1 \QuadDec:bQuadDec:quad_B_delayed_0\ \QuadDec:bQuadDec:quad_B_delayed_0\/clock_0 \QuadDec:bQuadDec:quad_B_delayed_0\/q 1.250
Route 1 \QuadDec:bQuadDec:quad_B_delayed_0\ \QuadDec:bQuadDec:quad_B_delayed_0\/q \QuadDec:bQuadDec:quad_B_delayed_1\/main_0 2.307
macrocell33 U(3,4) 1 \QuadDec:bQuadDec:quad_B_delayed_1\ HOLD 0.000
Clock Skew 0.000
\QuadDec:bQuadDec:quad_B_delayed_0\/q \QuadDec:bQuadDec:quad_B_filt\/main_0 3.557
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(2,4) 1 \QuadDec:bQuadDec:quad_B_delayed_0\ \QuadDec:bQuadDec:quad_B_delayed_0\/clock_0 \QuadDec:bQuadDec:quad_B_delayed_0\/q 1.250
Route 1 \QuadDec:bQuadDec:quad_B_delayed_0\ \QuadDec:bQuadDec:quad_B_delayed_0\/q \QuadDec:bQuadDec:quad_B_filt\/main_0 2.307
macrocell61 U(3,4) 1 \QuadDec:bQuadDec:quad_B_filt\ HOLD 0.000
Clock Skew 0.000
\QuadDec:bQuadDec:quad_B_delayed_2\/q \QuadDec:bQuadDec:quad_B_filt\/main_2 3.563
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell34 U(3,4) 1 \QuadDec:bQuadDec:quad_B_delayed_2\ \QuadDec:bQuadDec:quad_B_delayed_2\/clock_0 \QuadDec:bQuadDec:quad_B_delayed_2\/q 1.250
Route 1 \QuadDec:bQuadDec:quad_B_delayed_2\ \QuadDec:bQuadDec:quad_B_delayed_2\/q \QuadDec:bQuadDec:quad_B_filt\/main_2 2.313
macrocell61 U(3,4) 1 \QuadDec:bQuadDec:quad_B_filt\ HOLD 0.000
Clock Skew 0.000
\QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ce1_comb \QuadDec:Cnt16:CounterUDB:prevCompare\/main_0 3.603
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,2) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/clock \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ce1_comb 0.810
Route 1 \QuadDec:Cnt16:CounterUDB:cmp_out_i\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ce1_comb \QuadDec:Cnt16:CounterUDB:prevCompare\/main_0 2.793
macrocell56 U(3,2) 1 \QuadDec:Cnt16:CounterUDB:prevCompare\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART:BUART:rx_status_3\/main_5 6.932
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_15 Rx_1(0)/fb \UART:BUART:rx_status_3\/main_5 4.923
macrocell49 U(0,0) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_last\/main_0 6.932
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_15 Rx_1(0)/fb \UART:BUART:rx_last\/main_0 4.923
macrocell50 U(0,0) 1 \UART:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb MODIN1_1/main_2 6.940
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_15 Rx_1(0)/fb MODIN1_1/main_2 4.931
macrocell47 U(0,0) 1 MODIN1_1 HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb MODIN1_0/main_2 6.940
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_15 Rx_1(0)/fb MODIN1_0/main_2 4.931
macrocell48 U(0,0) 1 MODIN1_0 HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_0\/main_5 7.788
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_15 Rx_1(0)/fb \UART:BUART:rx_state_0\/main_5 5.779
macrocell41 U(0,1) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_2\/main_5 7.788
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_15 Rx_1(0)/fb \UART:BUART:rx_state_2\/main_5 5.779
macrocell44 U(0,1) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 12.525
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_15 Rx_1(0)/fb \UART:BUART:rx_postpoll\/main_0 4.931
macrocell6 U(0,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.235
datapathcell3 U(0,0) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_BusServo:BUART:sTX:TxShifter:u0\/cs_addr_0 3.044
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(2,0) 1 \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_BusServo:BUART:tx_bitclk_enable_pre\ \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_BusServo:BUART:sTX:TxShifter:u0\/cs_addr_0 2.854
datapathcell6 U(3,1) 1 \UART_BusServo:BUART:sTX:TxShifter:u0\ HOLD 0.000
Clock Skew 0.000
\UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_BusServo:BUART:txn\/main_5 3.339
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(2,0) 1 \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART_BusServo:BUART:tx_counter_dp\ \UART_BusServo:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_BusServo:BUART:txn\/main_5 3.149
macrocell71 U(3,1) 1 \UART_BusServo:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_BusServo:BUART:txn\/q \UART_BusServo:BUART:txn\/main_0 3.533
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell71 U(3,1) 1 \UART_BusServo:BUART:txn\ \UART_BusServo:BUART:txn\/clock_0 \UART_BusServo:BUART:txn\/q 1.250
macrocell71 U(3,1) 1 \UART_BusServo:BUART:txn\ \UART_BusServo:BUART:txn\/q \UART_BusServo:BUART:txn\/main_0 2.283
macrocell71 U(3,1) 1 \UART_BusServo:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_BusServo:BUART:sTX:TxShifter:u0\/so_comb \UART_BusServo:BUART:txn\/main_3 3.818
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(3,1) 1 \UART_BusServo:BUART:sTX:TxShifter:u0\ \UART_BusServo:BUART:sTX:TxShifter:u0\/clock \UART_BusServo:BUART:sTX:TxShifter:u0\/so_comb 1.510
Route 1 \UART_BusServo:BUART:tx_shift_out\ \UART_BusServo:BUART:sTX:TxShifter:u0\/so_comb \UART_BusServo:BUART:txn\/main_3 2.308
macrocell71 U(3,1) 1 \UART_BusServo:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_BusServo:BUART:tx_bitclk\/q \UART_BusServo:BUART:tx_state_1\/main_5 3.866
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell75 U(2,3) 1 \UART_BusServo:BUART:tx_bitclk\ \UART_BusServo:BUART:tx_bitclk\/clock_0 \UART_BusServo:BUART:tx_bitclk\/q 1.250
Route 1 \UART_BusServo:BUART:tx_bitclk\ \UART_BusServo:BUART:tx_bitclk\/q \UART_BusServo:BUART:tx_state_1\/main_5 2.616
macrocell72 U(3,3) 1 \UART_BusServo:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_BusServo:BUART:tx_bitclk\/q \UART_BusServo:BUART:tx_state_2\/main_5 3.869
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell75 U(2,3) 1 \UART_BusServo:BUART:tx_bitclk\ \UART_BusServo:BUART:tx_bitclk\/clock_0 \UART_BusServo:BUART:tx_bitclk\/q 1.250
Route 1 \UART_BusServo:BUART:tx_bitclk\ \UART_BusServo:BUART:tx_bitclk\/q \UART_BusServo:BUART:tx_state_2\/main_5 2.619
macrocell74 U(2,3) 1 \UART_BusServo:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_BusServo:BUART:tx_state_0\/q \UART_BusServo:BUART:tx_state_0\/main_1 4.361
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell73 U(3,4) 1 \UART_BusServo:BUART:tx_state_0\ \UART_BusServo:BUART:tx_state_0\/clock_0 \UART_BusServo:BUART:tx_state_0\/q 1.250
macrocell73 U(3,4) 1 \UART_BusServo:BUART:tx_state_0\ \UART_BusServo:BUART:tx_state_0\/q \UART_BusServo:BUART:tx_state_0\/main_1 3.111
macrocell73 U(3,4) 1 \UART_BusServo:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_BusServo:BUART:tx_state_2\/q \UART_BusServo:BUART:tx_state_1\/main_3 4.686
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell74 U(2,3) 1 \UART_BusServo:BUART:tx_state_2\ \UART_BusServo:BUART:tx_state_2\/clock_0 \UART_BusServo:BUART:tx_state_2\/q 1.250
Route 1 \UART_BusServo:BUART:tx_state_2\ \UART_BusServo:BUART:tx_state_2\/q \UART_BusServo:BUART:tx_state_1\/main_3 3.436
macrocell72 U(3,3) 1 \UART_BusServo:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_BusServo:BUART:tx_state_2\/q \UART_BusServo:BUART:tx_state_2\/main_3 4.694
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell74 U(2,3) 1 \UART_BusServo:BUART:tx_state_2\ \UART_BusServo:BUART:tx_state_2\/clock_0 \UART_BusServo:BUART:tx_state_2\/q 1.250
macrocell74 U(2,3) 1 \UART_BusServo:BUART:tx_state_2\ \UART_BusServo:BUART:tx_state_2\/q \UART_BusServo:BUART:tx_state_2\/main_3 3.444
macrocell74 U(2,3) 1 \UART_BusServo:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_BusServo:BUART:tx_state_2\/q \UART_BusServo:BUART:tx_bitclk\/main_3 4.694
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell74 U(2,3) 1 \UART_BusServo:BUART:tx_state_2\ \UART_BusServo:BUART:tx_state_2\/clock_0 \UART_BusServo:BUART:tx_state_2\/q 1.250
Route 1 \UART_BusServo:BUART:tx_state_2\ \UART_BusServo:BUART:tx_state_2\/q \UART_BusServo:BUART:tx_bitclk\/main_3 3.444
macrocell75 U(2,3) 1 \UART_BusServo:BUART:tx_bitclk\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 1.502
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell49 U(0,0) 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/clock_0 \UART:BUART:rx_status_3\/q 1.250
Route 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.252
statusicell2 U(0,0) 1 \UART:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_0\/main_8 3.403
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 MODIN4_6 \UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_0\/main_8 2.783
macrocell41 U(0,1) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_load_fifo\/main_5 3.403
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 MODIN4_6 \UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_load_fifo\/main_5 2.783
macrocell42 U(0,1) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_2\/main_7 3.403
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 MODIN4_6 \UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_2\/main_7 2.783
macrocell44 U(0,1) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_3\/main_5 3.444
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 MODIN4_6 \UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_3\/main_5 2.824
macrocell43 U(0,1) 1 \UART:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_2 \UART:BUART:rx_bitclk_enable\/main_0 3.516
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART:BUART:rx_count_2\ \UART:BUART:sRX:RxBitCounter\/count_2 \UART:BUART:rx_bitclk_enable\/main_0 2.896
macrocell45 U(0,0) 1 \UART:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_2 MODIN1_1/main_0 3.516
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART:BUART:rx_count_2\ \UART:BUART:sRX:RxBitCounter\/count_2 MODIN1_1/main_0 2.896
macrocell47 U(0,0) 1 MODIN1_1 HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_2 MODIN1_0/main_0 3.516
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART:BUART:rx_count_2\ \UART:BUART:sRX:RxBitCounter\/count_2 MODIN1_0/main_0 2.896
macrocell48 U(0,0) 1 MODIN1_0 HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_1 \UART:BUART:rx_bitclk_enable\/main_1 3.517
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART:BUART:rx_count_1\ \UART:BUART:sRX:RxBitCounter\/count_1 \UART:BUART:rx_bitclk_enable\/main_1 2.897
macrocell45 U(0,0) 1 \UART:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_1 MODIN1_1/main_1 3.517
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART:BUART:rx_count_1\ \UART:BUART:sRX:RxBitCounter\/count_1 MODIN1_1/main_1 2.897
macrocell47 U(0,0) 1 MODIN1_1 HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ Clock_Lim_DB
Source Destination Delay (ns)
Pin_Y_Lim(0)_PAD Net_378/main_0 16.979
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 Pin_Y_Lim(0)_PAD Pin_Y_Lim(0)_PAD Pin_Y_Lim(0)/pad_in 0.000
iocell31 P12[1] 1 Pin_Y_Lim(0) Pin_Y_Lim(0)/pad_in Pin_Y_Lim(0)/fb 7.630
Route 1 Net_432 Pin_Y_Lim(0)/fb Net_378/main_0 5.839
macrocell69 U(3,2) 1 Net_378 SETUP 3.510
Clock Clock path delay 0.000
Pin_X_Lim(0)_PAD Net_406/main_0 16.173
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 Pin_X_Lim(0)_PAD Pin_X_Lim(0)_PAD Pin_X_Lim(0)/pad_in 0.000
iocell30 P12[0] 1 Pin_X_Lim(0) Pin_X_Lim(0)/pad_in Pin_X_Lim(0)/fb 6.830
Route 1 Net_358 Pin_X_Lim(0)/fb Net_406/main_0 5.833
macrocell51 U(3,1) 1 Net_406 SETUP 3.510
Clock Clock path delay 0.000
Pin_Z_Lim(0)_PAD Net_408/main_0 15.493
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 Pin_Z_Lim(0)_PAD Pin_Z_Lim(0)_PAD Pin_Z_Lim(0)/pad_in 0.000
iocell32 P12[2] 1 Pin_Z_Lim(0) Pin_Z_Lim(0)/pad_in Pin_Z_Lim(0)/fb 7.315
Route 1 Net_382 Pin_Z_Lim(0)/fb Net_408/main_0 4.668
macrocell70 U(3,3) 1 Net_408 SETUP 3.510
Clock Clock path delay 0.000
+ Clock_Sw_DB
Source Destination Delay (ns)
Pin_Encoder_Sw(0)_PAD \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\/main_0 15.669
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 Pin_Encoder_Sw(0)_PAD Pin_Encoder_Sw(0)_PAD Pin_Encoder_Sw(0)/pad_in 0.000
iocell29 P1[5] 1 Pin_Encoder_Sw(0) Pin_Encoder_Sw(0)/pad_in Pin_Encoder_Sw(0)/fb 6.941
Route 1 Net_295 Pin_Encoder_Sw(0)/fb \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\/main_0 5.218
macrocell66 U(1,0) 1 \Debouncer_Enc_Sw:DEBOUNCER[0]:d_sync_0\ SETUP 3.510
Clock Clock path delay 0.000
+ CyBUS_CLK
Source Destination Delay (ns)
Pin_Quad_B(0)_PAD \QuadDec:bQuadDec:quad_B_delayed_0\/main_0 19.416
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 Pin_Quad_B(0)_PAD Pin_Quad_B(0)_PAD Pin_Quad_B(0)/pad_in 0.000
iocell28 P1[6] 1 Pin_Quad_B(0) Pin_Quad_B(0)/pad_in Pin_Quad_B(0)/fb 7.843
Route 1 Net_245 Pin_Quad_B(0)/fb \QuadDec:bQuadDec:quad_B_delayed_0\/main_0 8.063
macrocell32 U(2,4) 1 \QuadDec:bQuadDec:quad_B_delayed_0\ SETUP 3.510
Clock Clock path delay 0.000
Pin_Quad_A(0)_PAD \QuadDec:bQuadDec:quad_A_delayed_0\/main_0 16.312
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 Pin_Quad_A(0)_PAD Pin_Quad_A(0)_PAD Pin_Quad_A(0)/pad_in 0.000
iocell27 P1[7] 1 Pin_Quad_A(0) Pin_Quad_A(0)/pad_in Pin_Quad_A(0)/fb 7.089
Route 1 Net_244 Pin_Quad_A(0)/fb \QuadDec:bQuadDec:quad_A_delayed_0\/main_0 5.713
macrocell29 U(1,1) 1 \QuadDec:bQuadDec:quad_A_delayed_0\ SETUP 3.510
Clock Clock path delay 0.000
+ Clock To Output Section
+ Clock_1(fixed-function)
Source Destination Delay (ns)
\PWM_Spindle:PWMHW\/cmp Pin_Spindle(0)_PAD 20.207
Type Location Fanout Instance/Net Source Dest Delay (ns)
timercell F(Timer,0) 1 \PWM_Spindle:PWMHW\ \PWM_Spindle:PWMHW\/clock \PWM_Spindle:PWMHW\/cmp 1.000
Route 1 Net_501 \PWM_Spindle:PWMHW\/cmp Pin_Spindle(0)/pin_input 3.748
iocell23 P0[2] 1 Pin_Spindle(0) Pin_Spindle(0)/pin_input Pin_Spindle(0)/pad_out 15.459
Route 1 Pin_Spindle(0)_PAD Pin_Spindle(0)/pad_out Pin_Spindle(0)_PAD 0.000
Clock Clock path delay 0.000
+ Clock_Step_Pulse
Source Destination Delay (ns)
\Control_Reg_Step:Sync:ctrl_reg\/control_2 Pin_Step_Z(0)_PAD 24.101
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(3,3) 1 \Control_Reg_Step:Sync:ctrl_reg\ \Control_Reg_Step:Sync:ctrl_reg\/clock \Control_Reg_Step:Sync:ctrl_reg\/control_2 1.210
Route 1 Net_82 \Control_Reg_Step:Sync:ctrl_reg\/control_2 Pin_Step_Z(0)/pin_input 7.043
iocell20 P15[4] 1 Pin_Step_Z(0) Pin_Step_Z(0)/pin_input Pin_Step_Z(0)/pad_out 15.848
Route 1 Pin_Step_Z(0)_PAD Pin_Step_Z(0)/pad_out Pin_Step_Z(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_Step:Sync:ctrl_reg\/control_1 Pin_Step_Y(0)_PAD 22.798
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(3,3) 1 \Control_Reg_Step:Sync:ctrl_reg\ \Control_Reg_Step:Sync:ctrl_reg\/clock \Control_Reg_Step:Sync:ctrl_reg\/control_1 1.210
Route 1 Net_496 \Control_Reg_Step:Sync:ctrl_reg\/control_1 Pin_Step_Y(0)/pin_input 5.786
iocell11 P0[1] 1 Pin_Step_Y(0) Pin_Step_Y(0)/pin_input Pin_Step_Y(0)/pad_out 15.802
Route 1 Pin_Step_Y(0)_PAD Pin_Step_Y(0)/pad_out Pin_Step_Y(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_Step:Sync:ctrl_reg\/control_0 Pin_Step_X(0)_PAD 22.382
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(3,3) 1 \Control_Reg_Step:Sync:ctrl_reg\ \Control_Reg_Step:Sync:ctrl_reg\/clock \Control_Reg_Step:Sync:ctrl_reg\/control_0 1.210
Route 1 Net_442 \Control_Reg_Step:Sync:ctrl_reg\/control_0 Pin_Step_X(0)/pin_input 5.921
iocell21 P0[0] 1 Pin_Step_X(0) Pin_Step_X(0)/pin_input Pin_Step_X(0)/pad_out 15.251
Route 1 Pin_Step_X(0)_PAD Pin_Step_X(0)/pad_out Pin_Step_X(0)_PAD 0.000
Clock Clock path delay 0.000
+ CyBUS_CLK
Source Destination Delay (ns)
\Control_Reg_Dir:Sync:ctrl_reg\/control_1 Pin_Dir_Y_1(0)_PAD 23.823
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,4) 1 \Control_Reg_Dir:Sync:ctrl_reg\ \Control_Reg_Dir:Sync:ctrl_reg\/busclk \Control_Reg_Dir:Sync:ctrl_reg\/control_1 2.050
Route 1 Net_107 \Control_Reg_Dir:Sync:ctrl_reg\/control_1 Pin_Dir_Y_1(0)/pin_input 6.278
iocell10 P0[7] 1 Pin_Dir_Y_1(0) Pin_Dir_Y_1(0)/pin_input Pin_Dir_Y_1(0)/pad_out 15.495
Route 1 Pin_Dir_Y_1(0)_PAD Pin_Dir_Y_1(0)/pad_out Pin_Dir_Y_1(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Step_Enable:Sync:ctrl_reg\/control_0 Stepper_Enable_Pin(0)_PAD 23.410
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,1) 1 \Control_Step_Enable:Sync:ctrl_reg\ \Control_Step_Enable:Sync:ctrl_reg\/busclk \Control_Step_Enable:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_708 \Control_Step_Enable:Sync:ctrl_reg\/control_0 Stepper_Enable_Pin(0)/pin_input 5.435
iocell33 P15[5] 1 Stepper_Enable_Pin(0) Stepper_Enable_Pin(0)/pin_input Stepper_Enable_Pin(0)/pad_out 15.925
Route 1 Stepper_Enable_Pin(0)_PAD Stepper_Enable_Pin(0)/pad_out Stepper_Enable_Pin(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_Dir:Sync:ctrl_reg\/control_1 Pin_Dir_Y(0)_PAD 23.351
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,4) 1 \Control_Reg_Dir:Sync:ctrl_reg\ \Control_Reg_Dir:Sync:ctrl_reg\/busclk \Control_Reg_Dir:Sync:ctrl_reg\/control_1 2.050
Route 1 Net_107 \Control_Reg_Dir:Sync:ctrl_reg\/control_1 Pin_Dir_Y(0)/pin_input 6.278
iocell18 P0[5] 1 Pin_Dir_Y(0) Pin_Dir_Y(0)/pin_input Pin_Dir_Y(0)/pad_out 15.023
Route 1 Pin_Dir_Y(0)_PAD Pin_Dir_Y(0)/pad_out Pin_Dir_Y(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_Dir:Sync:ctrl_reg\/control_2 Pin_Dir_Z(0)_PAD 23.194
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,4) 1 \Control_Reg_Dir:Sync:ctrl_reg\ \Control_Reg_Dir:Sync:ctrl_reg\/busclk \Control_Reg_Dir:Sync:ctrl_reg\/control_2 2.050
Route 1 Net_108 \Control_Reg_Dir:Sync:ctrl_reg\/control_2 Pin_Dir_Z(0)/pin_input 5.583
iocell17 P0[6] 1 Pin_Dir_Z(0) Pin_Dir_Z(0)/pin_input Pin_Dir_Z(0)/pad_out 15.561
Route 1 Pin_Dir_Z(0)_PAD Pin_Dir_Z(0)/pad_out Pin_Dir_Z(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_Dir:Sync:ctrl_reg\/control_0 Pin_Dir_X(0)_PAD 22.464
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,4) 1 \Control_Reg_Dir:Sync:ctrl_reg\ \Control_Reg_Dir:Sync:ctrl_reg\/busclk \Control_Reg_Dir:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_110 \Control_Reg_Dir:Sync:ctrl_reg\/control_0 Pin_Dir_X(0)/pin_input 5.534
iocell19 P0[4] 1 Pin_Dir_X(0) Pin_Dir_X(0)/pin_input Pin_Dir_X(0)/pad_out 14.880
Route 1 Pin_Dir_X(0)_PAD Pin_Dir_X(0)/pad_out Pin_Dir_X(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_BusServo_IntClock
Source Destination Delay (ns)
\UART_BusServo:BUART:txn\/q Pin_BusServoTx(0)_PAD 31.673
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell71 U(3,1) 1 \UART_BusServo:BUART:txn\ \UART_BusServo:BUART:txn\/clock_0 \UART_BusServo:BUART:txn\/q 1.250
Route 1 \UART_BusServo:BUART:txn\ \UART_BusServo:BUART:txn\/q Net_879/main_0 3.925
macrocell24 U(3,3) 1 Net_879 Net_879/main_0 Net_879/q 3.350
Route 1 Net_879 Net_879/q Pin_BusServoTx(0)/pin_input 7.481
iocell34 P2[0] 1 Pin_BusServoTx(0) Pin_BusServoTx(0)/pin_input Pin_BusServoTx(0)/pad_out 15.667
Route 1 Pin_BusServoTx(0)_PAD Pin_BusServoTx(0)/pad_out Pin_BusServoTx(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_IntClock
Source Destination Delay (ns)
\UART:BUART:txn\/q Tx_1(0)_PAD 31.531
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(2,4) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q Net_14/main_0 2.595
macrocell1 U(2,4) 1 Net_14 Net_14/main_0 Net_14/q 3.350
Route 1 Net_14 Net_14/q Tx_1(0)/pin_input 7.369
iocell9 P12[7] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 16.967
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000
+ Asynchronous Constraints
+ Recovery
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\QuadDec:Net_1260\/q \QuadDec:Cnt16:CounterUDB:sSTSReg:stsreg\/reset 150.083 MHz 6.663 35.004
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell62 U(3,2) 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/clock_0 \QuadDec:Net_1260\/q 1.250
Route 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/q \QuadDec:Cnt16:CounterUDB:sSTSReg:stsreg\/reset 5.413
statusicell6 U(2,3) 1 \QuadDec:Cnt16:CounterUDB:sSTSReg:stsreg\ RECOVERY -0.000
Clock Skew 0.000
+ Removal
Source Destination Slack (ns) Violation
\QuadDec:Net_1260\/q \QuadDec:Cnt16:CounterUDB:sSTSReg:stsreg\/reset 6.663
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell62 U(3,2) 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/clock_0 \QuadDec:Net_1260\/q 1.250
Route 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/q \QuadDec:Cnt16:CounterUDB:sSTSReg:stsreg\/reset 5.413
statusicell6 U(2,3) 1 \QuadDec:Cnt16:CounterUDB:sSTSReg:stsreg\ REMOVAL 0.000
Clock Skew 0.000